In digital wireless communications systems, it is often desirable for multiple (i.e., more than two) terminals to communicate with one another, all sharing a single frequency. One method of accomplishing this is commonly known as TDMA, or Time Division Multiple Access, whereby communications occur in a series of consecutive "frames". A frame is a prescribed block of time, (e.g., 10 milliseconds) during which each terminal is permitted to transmit and receive. All communications over the TDMA system are synchronized to the repetition rate of the series of frames. Each terminal is assigned one or more time-slots within a frame (a time slot is a portion of the duration of the frame) during which it may transmit or receive. Usually, a terminal is assigned at least two time slots: one time slot for transmitting and another time slot for receiving. Another time slot may be assigned to the terminal for energy measurement or for special signalling purposes. (Presumably, each terminal's time slot for transmitting is allocated to another terminal for receiving, and vice-versa). After the completion of one frame, another frame begins, such that frames occur sequentially in time, and such that during each frame, each terminal has an opportunity to transmit and receive short "bursts" of data during its assigned time slots. An exemplary time-sliced arrangement is shown in FIGS. 1A and 1B.
FIG. 1A depicts a time-line 100 having a generalized organization of frames and time slots for a TDMA wireless communication system. As a "previous" frame 110A (Frame N-1) ends, a "current" frame 110B (Frame N) commences. As the current frame 110B ends, a "next" frame 110C (Frame N+1) commences, etc. Within each frame 110A, 110B and 110C (of which the current frame 110B is representative), a plurality of shorter time slots (three being shown) are defined. In much the same sequential manner that frames follow one another in time, time slots follow one another in time (see time-line 110). For example, three time slots 120A (Slot M-1), 120B (Slot M) and 120C (Slot M+1) follow one another in time.
In order for a terminal to transmit, receive, make energy measurements or perform any other kind of signalling during a time slot, the terminal must control a wireless transceiver in a tightly synchronized manner. For example, in order to transmit during an assigned time slot, a terminal must wait for the assigned time slot to come along, then the terminal must enable its transceiver into a "transmit" mode, and must wait for the transmitter circuitry to settle (if any settling time is required). Next, the terminal must provide data to be transmitted at a transmit input to the transceiver. After transmitting the data (or at the end of the time-slot) the terminal must disable the transmit mode of the transceiver so that other terminals can communicate during their assigned time slots.
In order to communicate over a TDMA communication system, it is necessary that each terminal generate a set of frame- and time-slot synchronized real-time control signals for operating its transceiver and any other relevant communications-related apparatus. Examples of such real-time control signals might be: "enable transmitter power", "enable transmitter output", "disable receiver input", etc.
A TDMA system needs to effect operation of these control signals (e.g., "turn on the transmitter") to precise timing within a frame and a slot. This control is accomplished by activating and deactivating signals in a frame and time slot in a bit-time synchronous manner. Since actual signal timing requirements vary between different implementations of TDMA systems, the real-time control signal generation mechanism must allow for at least some flexibility in the timing definition.
FIG. 1B is a time-line 102 showing an expansion of time slot "M" 120B, during which two arbitrarily chosen, but representative, control signals 130 and 140 are operated by a terminal device. Time slot M is further subdivided into a number of smaller "bit times" 150. After the beginning of slot "M" 120B, a terminal waits until a first bit time t1 151 and asserts control signal 130. At a second bit time t2 152, the terminal asserts control signal 140, de-asserting it at a third bit time t3 153. At a fourth bit time t4 154, the terminal de-asserts the control signal 130. At a fifth bit time t5 155, the terminal asserts the control signal 140, de-asserting it at a sixth bit time t6 156.
The control signals 130 and 140 shown in FIG. 1B are merely representative of a wide variety of possible control signals, and are shown for purposes of illustration only. Actual control signals in a TDMA wireless communication system would depend upon terminal and transceiver configuration and upon exact frame, slot and bit time definitions for the specific TDMA wireless communication system of interest.
An example of a TDMA wireless system is known as the "DECT" system. In the exemplary DECT system, twelve full duplex communications channels share a single frequency by dividing the transmission time into "Frames", "Slots", and "Bits". A DECT frame is 10 milliseconds long; it is further divided into 24 equal time slots (slot 0 to slot 23). Each time slot is further divided into 420 Bit-times. Each Bit-time is the time required to transmit one bit of digital information.
Prior-art techniques for generation of real-time control signals in TDMA wireless communications systems include techniques utilized by Sitel (Sierra) and Philips, discussed in greater detail hereinbelow. In order to make the ensuing discussion of TDMA systems clear, the following conventions will be used:
A real-time "event" is a frame, slot and bit synchronized change of state of a control signal. PA1 A "frame program" is a stored set of instructions for defining a set of real-time events. PA1 An RF (Radio Frequency) Front-end contains circuitry that transmits and receives radio frequency (RF) signals. PA1 A Burst Mode Controller (BMC) controls the timing of the RF Front-end and extracts digital data therefrom. PA1 1) an RF (Radio Frequency) Front-end (transceiver); PA1 2) a Burst Mode Controller (BMC); and PA1 3) a Micro-controller.
A Micro-controller contains a program that includes instructions for implementing high-level communications protocols and lower-level instructions for controlling a BMC.
The basic elements of interest in a TDMA system include:
Sitel (Sierra) 14400/14401 BMC
Sitel's 14400 and 14401 Burst Mode Controllers contain a relatively large on-chip block of RAM (Random Access Memory) for storing "Frame Programs" that control the generation of real-time events to be generated. A separate (external) micro-controller prepares these programs and loads them to the BMC (e.g., into a RAM block) before the sequence of events is to begin. The Sitel devices also contain a "Sequencer" that interprets the commands in the frame programs and executes them, one instruction every bit-time. The instructions tell the BMC to set a signal, clear a signal, issue an interrupt, etc. In order to limit the size of each instruction (and thus limit the size of the RAM block), the instructions are limited to effecting only single events. In the Sitel system, the microcontroller controls a communication channel during a time slot by copying a frame program from the microcontroller's local memory to the BMC's internal RAM.
FIG. 2 is a block diagram of such a prior-art Sitel-type TDMA wireless communications terminal 200. A back-end processor (BEP) 202 communicates with an RF Front end 240 for effecting TDMA wireless digital communication (via an antenna 242) with other similar terminals. The BEP 202 includes a microcontroller 210, a BMC 220 and an ADPCM (Adaptive Delta Pulse Code Modulation) encoder/decoder and codec 230. The ADPCM encoder/decoder and codec 230 connects to a speaker 232 and a microphone 234, e.g., as in a telephone handset. The microcontroller includes internal ROM (Read Only Memory) 212 and RAM (Random Access Memory) 214, and I/O Ports 216. The I/O ports 216 interface the microcontroller 210 to a display 217 and to a keyboard 218.
The BMC 220 (which is implemented as a discrete chip) includes an on-chip RAM 222 for storing a frame program. The frame program in the on-chip RAM 222 is interpreted by a complex sequence generator 224 to generate real-time events (e.g., transmitter control, interrupts, etc.). A Data interface (Data I/F) 226 in the BMC controls the exchange of transmitted and receive data with the RF Front End 240. The main drawbacks of such an approach are that it necessitates a large chip area for the BMC (220) due to the on-chip RAM and complex sequencer; and that flexibility in controlling events is significantly limited, since only one event (control signal state change) can be effected at a time.
Philips BMC
The Philips BMC uses a different method of generating real-time events. It contains a register for each of the events to be generated. The value stored in each register determines (within a limited range of bit times) the start and stop time of a respective event. The main drawbacks of this approach are: limited flexibility in controlling real-time events, since only a limited range of bit times can be specified for any given event; and the registers must be re-programmed for each active slot (i.e., transmit slot, receive slot, energy measurement slot, etc.).